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- clock pulse gate 同步脉冲开关
- Trigger control circuit from complex programmable logic device (CPLD), ICL7135CN, the clock pulse circuit and optocoupler inverter constituted. 触发控制电路由复杂可编程逻辑器件（CPLD）,ICL7135CN,时钟脉冲电路、反相器和光耦构成。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时，（或者在最后一个时钟脉冲的下降沿之后）主机将时钟拉低，键盘/鼠标不必重新传输任何数据。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/ mouse does not need to retransmit any data. 如果在第一个高->时钟跳变时，（者在最后一个时钟脉冲的下降沿之后）机将时钟拉低，键盘/标不必重新传输任何数据。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the a last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时，（或者在最后一个时钟脉冲的下降沿之后）主机将时钟拉低，键盘/鼠标不必重新传输任何数据。
- The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register. 触发器的并行加载可以是同步的（即在时钟脉冲到达时发生）或异步的（不依赖于时钟），这取决于移位寄存器的设计。
- Note that a set of lights attached to O1, O2, O3 would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse. 注意，一组接在O1,O2,O3上的灯泡将以二进制（模8）形式显示第一个脉冲以来已完成的完整时钟脉冲数。
- In this thesis, a placer based on optimizing the power consumption of clock gating network is presented. 本论文研制之电路摆置器，乃基于将用于低功耗设计下之闸控制时脉网路之功率消耗最佳化。
- Clock gating is an efficient way of reducing dynamic power consumption in digital circuits. 时钟闸控是降低数位电路动态功率消耗的有效方法。
- A microprocessor designer may decide to make all instructions last five clock pulses. 微处理机设计人员可以决定使所有的指令持续五个时钟脉冲。
- It is always a good idea to invest the time at the beginning to understand the clock structure and the clock gating in your design. 在设计一开始首先了解其时钟结构和门控时钟是一个不错的想法。
- This paper analyses the disadvantages of many clock gating techniques and points out that they are obstacles in System-on-Chip(SoC) design. 门控时钟技术一直以来是降低芯片动态功耗的有效方法。
- Programmable output clock pulse width 输出脉冲宽度可编程
- A man appeared at the castle gate in the guise of a woodcutter. 一个男子打扮成樵夫的模样出现在城堡的门口。
- suppressed clock pulse duration modulation 压缩时钟脉冲宽度调制
- Did you remember to padlock the gate? 你是否记得用挂锁把大门锁上？
- multiphase clock pulse generator 多相时钟脉冲发生器
- I saw him make by the gate on his bicycle. 我看见他骑自行车从大门旁边过去了。
- In binary synchronous communication, the use of clock pulses to control synchron ization of data and control characters. 在二进制位同步通信中,使用时钟脉冲来控制数据和控制字符的同步。
- The truck came to a dead stop out of the gate. 那辆卡车在大门外突然停下。
